On-die termination (ODT) is a technology that improves signal integrity on a transmission line by establishing internal termination resistance for one or more devices. This terminal resistance prevents transition points that connect the one or more devices to the transmission line from causing reflection on the transmission line, resulting in noise. Devices can have internal ODT control logic to control whether to perform an ODT operation and how much internal termination resistance to apply.
Computing systems that use have a memory apparatus on the same transmission line as other memory apparatus or other components are instances in which ODT operations are typically used. When one component is performing an operation that uses a transmission line common to the memory apparatus, the memory apparatus is instructed to perform an ODT operation so that it does not interfere with the signal on the transmission line. In some implementations, this instruction to the memory apparatus is issued by setting an ODT pin on the memory apparatus to high when an ODT operation is needed (e.g. when the memory apparatus is not using the transmission line) and setting the ODT pin on the memory apparatus to low when an ODT operation is not needed (e.g. when the memory apparatus is using the transmission line, such as during a read or write operation). In some implementations, other ODT settings can override a nominal ODT setting, such as when dynamic ODT is active for a write operation.
Some memory systems use a delay-locked loop (DLL) circuit to calibrate an input clock to a correct phase. A DLL circuit can have multiple exit points, one of which can be selected when the DLL circuit is initialized to set what phase delay the DLL circuit will implement. When a memory apparatus uses a DLL circuit for an input clock, it shifts the input clock into a DLL domain. Any ODT instructions must also be shift into the DLL domain so that the resulting internal termination resistance will be applied with the correct timing. Signals described as “in a domain” may be synchronized such that signals in the same domain are synchronized to a common clock for the domain.
Some memory systems, such as the memory system 100 shown in FIG. 1, use a DLL delay line 180 to delay an input clock received on a CLKS 106 line in a first domain 150 and output on DLL line 110 in a DLL domain 160. In some implementations, the clock signal can be passed through a CLKS gate 170, which passes the clock signal from CLKS line 104 onto CLKS line 106 when CMD line 103 has a control signal indicating conditions such as a read, write, or ODT operation is in progress.
To synchronize ODT information received on Rtt CMD line 102, a clone 175 of the DLL delay line, for nominal ODT, is used to delay the ODT information to be in the DLL domain 160. Delayed ODT information is output on delayed Rtt CMD line 108. The delayed ODT information on delayed Rtt CMD line 108 can be shifted by RttNom shifter 185, using the delayed clock signal on DLL line 110, by an amount specified by a mode register (not shown). This shift may configure the ODT information to match, e.g., an amount of write latency of the memory system 100. RttNom shifter 185 can produce shifted and delayed ODT information on shifted and delayed Rtt CMD line 112. The shifted and delayed ODT information can control whether ODT termination is enabled at the memory system's I/O pins (DQ), which can be overridden by other ODT signals, e.g. when dynamic ODT is active.
The techniques introduced here may be better understood by referring to the following Detailed Description in conjunction with the accompanying drawings, in which like reference numerals indicate identical or functionally similar elements.